Dr Bill Gavin
Embedded-ML / edge-AI engineer · PhD, embedded machine learning
Lytham St. Annes, Lancashire, UK · remote preferred, open to hybrid or relocation · billjgavin@gmail.com · LinkedIn
Profile
PhD-qualified embedded-ML engineer specialising in hardware-efficient AI for real-time signal processing. Built a novel FPGA modulation-classification and SNR-estimation system that reaches deep-learning-level accuracy with zero RAM and state-of-the-art inference latency, published in IEEE. Expert in digital hardware design (Verilog), algorithm optimisation, and ML inference on resource-constrained systems. Builds whole systems, from the driver layer to the web UI, with testing designed in from the start, and clean contracts and documentation so a team can extend the work. Seeking edge-AI and embedded-ML roles, and broader ML or systems work; remote preferred, open to hybrid or relocation for the right team.
Skills
Embedded ML Edge AI Verilog FPGA Python MATLAB On-device LLM PyTorch TinyML C / Embedded C BLE Linux Test-driven systems
Education
PhD: Embedded Machine Learning for Wireless Communications
University of Sheffield · Nov 2021 – Jun 2025
MEng Digital Electronics, First Class Honours
University of Sheffield · Sept 2016 – Jun 2020
Experience
PhD Researcher: Real-Time Edge AI for Wireless Communications
University of Sheffield · Nov 2021 – Jun 2025
- Designed an FPGA system performing simultaneous automatic modulation classification (AMC) and SNR estimation in a single unified architecture, delivering two capabilities in the hardware footprint usually required for one.
- Matched state-of-the-art deep-learning classification accuracy while eliminating RAM entirely, enabling deployment on severely resource-constrained hardware.
- Developed a novel O(n) sorting algorithm to enable a fully pipelined DBSCAN on FPGA, preserving O(n) complexity while processing a continuous real-time data stream, a previously unreported capability.
- Reached state-of-the-art inference latency through a fully pipelined datapath with no buffering bottleneck: a 7.5× latency improvement over the next fastest comparable design and 71.7% greater power efficiency than existing approaches.
- Published in IEEE Open Journal of the Computer Society (2024) and presented at the SAI Computing Conference, London (2023).
Independent Project: Smart Van + full campervan conversion
Self-directed · 2025 – 2026
- Built a bespoke edge-AI control system on a Jetson Orin Nano: a local voice agent, Victron BLE power telemetry, all-local inference, and a custom FastAPI web dashboard, with design-for-testing throughout.
- Converted a bare commercial van into a complete live-in vehicle over roughly a year to a fixed budget: LPG, 12V electrical, fresh and grey water plumbing, and full thermal insulation.
- Designed and built bespoke interior joinery, and managed the full project lifecycle independently: specification, structural planning, procurement, budgeting, and build sequencing.
MEng Final-Year Projects
University of Sheffield · 2019 – 2020
- Drone RF detection: built an MLP classifier to identify drone communications in a mixed RF environment, distinguishing control signals from background Wi-Fi and phone traffic, an early application of ML to real-world spectrum awareness.
- Minimal AES-128 on FPGA: reproduced and validated the smallest known hardware AES implementation from the literature, targeting minimum logic area.
Publications
- B. Gavin, T. Deng, and E. Ball, "Low area and low power FPGA implementation of a DBSCAN-based RF modulation classifier," IEEE Open Journal of the Computer Society, vol. 5, 2024. DOI: 10.1109/OJCS.2024.3355693
- B. Gavin, T. Deng, and E. A. Ball, "A Novel Method of Automatic Modulation Classification with an Optimised 1D DBSCAN," Intelligent Computing, Proceedings of the 2023 Computing Conference (SAI), Lecture Notes in Networks and Systems, vol. 711, Springer, London, 2023. DOI: 10.1007/978-3-031-37717-4_63
- Y. Zhao, T. Deng, B. Gavin, E. A. Ball, and L. Seed, "A Ultra-Low Cost and Accurate AMC Algorithm and Its Hardware Implementation," IEEE Open Journal of the Computer Society, vol. 6, pp. 460–467, 2025. DOI: 10.1109/OJCS.2024.3381827