Why build it
Cognitive radio and 5G/6G receivers need to know what they are listening to: which modulation scheme a signal uses, and how clean it is. Deep-learning classifiers do this accurately but are far too heavy for the small, low-power hardware at the edge of a network. The goal of the PhD was to reach that same accuracy in a tiny, RAM-free FPGA design that classifies a live signal stream in real time.
The approach
Two jobs, one core
Automatic modulation classification and non-data-aided SNR estimation share a single unified architecture, delivering both capabilities in the footprint usually spent on one.
1D DBSCAN decomposition
The 2D constellation is split into two 1D datasets and clustered with DBSCAN, which separates even same-order schemes like 4QAM and 4PSK that other methods confuse.
Pipelined O(n) sort
A novel pipelined insertion sort keeps the whole DBSCAN at O(n) on a continuous real-time stream with no latency overhead, a previously unreported capability on FPGA.
Zero-RAM datapath
A fully pipelined datapath with no buffering bottleneck and no RAM, synthesised in Vivado across four configurations from DBMC-50 up to DBMC-1000.
What it achieved
The design matched state-of-the-art deep-learning classification accuracy while eliminating RAM entirely. Against the next fastest comparable design it cut inference latency by 7.5×, and against existing approaches it ran 71.7% more power-efficiently. It sustains roughly 142,857 classifications per second and reaches 100% accuracy at SNR of 8dB or above on 5G modulation sets.
The work was published in the IEEE Open Journal of the Computer Society (2024) and presented at the SAI Computing Conference in London (2023).
FPGA Verilog MATLAB Vivado DSP Published in IEEE
Read the research
The full method, hardware results, and comparisons are in the thesis, with the Verilog, MATLAB, and Python on GitHub.